When a clock generator in an electronic device generates a single frequency, emission of this frequency and higher harmonics increases. For this reason, use is made of a spread spectrum clock generator (SSCG) that reduces the peak of unnecessary emissions by frequency modulation and diminishes EMI (electromagnetic interference).
Operating frequencies have risen in recent years and the problem of bit-to-bit skew in a parallel bus has become more conspicuous. This has led to the widespread use of serial interfaces which are free of bit-to-bit skew and such serial interfaces have come to be employed also in personal computers in general use. For example, SATA (Serial ATA) is used as the interface standard between a hard disk and a CPU. SATA is a serial interface standard in which the first-generation communication speed is 1.5 Gbps and incorporates a spread spectrum clock (SSC) standard as an EMI countermeasure in order to be used in personal computers and the like.
In general, a PLL (phase-locked loop) using a pulse-swallow frequency divider is employed as an SSCG. However, an SSCG that employs a phase interpolator and a controller and not a pulse-swallow frequency divider and VCO (voltage-controlled oscillator) also is known in the art (see Patent Document 1 field by the present applicant). An example of structure in line with the SSC standard of SATA (third example) is illustrated in Patent Document 1. However, the compression of logic in a controller that generates a down signal is difficult with a combination of counters, and it is difficult to reduce the scale of the circuitry. It is necessary, therefore, to consider a combination with which the compression pf logic is possible. This will be described below.
Disclosed in Patent Document 1 is an example (the third example in Patent Document 1) well suited to the SSC standard (degree of modulation: 0 to −5000 ppm; modulation frequency: 30 to 33 kHz) of SATA. FIG. 9 is a diagram illustrating the arrangement disclosed in Patent Document 1. The arrangement includes a phase interpolator 4 which receives an input signal from an input terminal 1 and outputs an output clock signal the phase of which has been varied based upon a phase control signal, and an SSC (spread spectrum clock) controller 3′ which supplies a phase control signal (down signal 6) to the phase interpolator 4 to frequency-modulate the output clock from an output terminal 2. The SSC controller 3′ has a pre-divider 21, a p-counter 22′, an up/down counter 23′ and a controller 24′. The down signal 6 is supplied to the phase interpolator 4 from the controller 24′, the frequency of occurrence of a delay Δ (see FIG. 10) of a prescribed amount with respect to the clock signal that is supplied to the input terminal 1 is controlled and a modulated clock is output from the output terminal 2, thereby implementing an SSCG suited to a standard referred to as “downspread”.
In Patent Document 1, the phase step of the phase interpolator 4 in FIG. 9 is assumed to be 1/64 [resolution N=64, in which case period T0 of the input clock signal= 1/64 of 1/(1.5 GHz) holds] and the frequency dividing ratio of a pre-divider 21 is assumed to be 4. A conditional equation for meeting the SATA standard is as follows:1500/0.033≦2×m×p×u≦1500/0.03  (1)With regard to a count p in a p-counter 22 and a count u in an up/down counter 23, a value that satisfies this equation is assumed to be 77, and the modulation frequency is assumed to be 31.62 Hz.
The p-counter 22′ produces an output signal 25 whenever it counts 77 times. Upon receiving this signal, the up/down counter 23′ updates the value u. Based upon the combination of the value in p-counter 22′ and the value in up/down counter 23′, the controller 24′ generates the down signal 6. FIG. 11 is a diagram illustrating 77×78 combinations of generation of the down signal 6. The count value p in p-counter 22′ is indicated along the horizontal direction. Up-counting of 0 to 77 by the up/down counter 23′ is indicated along the vertical direction in the upper half of FIG. 11, and down-counting of 77 to 0 by the up/down counter 23′ is indicated along the vertical direction in the lower half of FIG. 11. Further, n1 is the number of logical “1”s in down signal 6 that are output from the controller 24′ in a time period of a reference period number k (=m×p). The time period of the reference period number k, which is stipulated by the product of one period of the input clock signal and the reference period number k, is termed a reference period.
As illustrated in FIG. 11, the number n1 of logical “1”s of down signal 6 in the time period of the reference period number k (=m×p) is successively incremented, the frequency of occurrence of the phase delay of the phase step 1/64 (resolution N=64) of the phase interpolator 4 is raised, and the value u in the up/down counter 23′ is counted up successively from 0. When u=77 holds, n1 is made 77 and the controller 24′ applies maximum modulation to the output clock from output terminal 2. The value u in up/down counter 23′ is subsequently counted down and n1 is successively decremented, thereby changing average frequency f in the time period of the reference period number k (=m×p).
If the phase step of the phase interpolator 4 is 1/N (= 1/64) of one period T0 of the clock signal at the input terminal and the average period of the clock signal when the number of down signals 6 in the time period of the reference period number k is n is represented by T<average>, then we have k×T<average>=k×T0+(n/N)×T0 and the average frequency f<average> is
                              f                      <            average            >                          =                  k          /                      [                                          k                ×                                  T                  0                                            +                                                (                                      n                    /                    N                                    )                                ×                                  T                  0                                                      ]                                                  =                              (                          1              /                              T                0                                      )                    ×                                    (                              k                ×                N                            )                        /                          (                                                k                  ×                  N                                +                n                            )                                          
As illustrated in FIG. 12, the modulated waveform according to the above-mentioned combination is that obtained by modulation at a modulation frequency of 31.62 kHz. A single modulation period Tfm is given by 2×m×p×u×T0, and we have Tfm=31.6 μs from m=4, p=u=77, 1.5 GHz=1/T0. That is, this is a triangular wave in which the maximum modulation frequency is 1.5 GHz (=1500 MHz) and the minimum modulation frequency is 1494.2 MHz.    [Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2005-4451 (Pages 5 to 9, 11 to 13, FIGS. 1, 3 and 4)